Design-Reuse

Verilog register file IP Listing

IGMDLRX01A is an asynchronous read and synchronous write ULVT periphery two port register file compiler (2PRF). It is developed with TSMC 6nm 0.75V/1.8V CMOS LOGIC FinFET Process. Different ... The ...
Hackaday

Learning Verilog For FPGAs: Flip Flops

Last time I talked about how to create an adder in Verilog with an eye to putting it into a Lattice iCEstick board. The adder is a combinatorial circuit and didn’t use a clock. This time, we’ll finish ...
EDN

An overview of SystemVerilog 3.1

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
Design-Reuse

TSMC Verilog register file IP Listing

IGMDLRX01A is an asynchronous read and synchronous write ULVT periphery two port register file compiler (2PRF). It is developed with TSMC 6nm 0.75V/1.8V CMOS LOGIC FinFET Process. Different ... The ...