Duke Pratt School of Engineering

Study Finds Next-Generation Transistor Performance Inflated in Most Lab Testing

Duke engineers show how a common device architecture used to test 2D transistors overstates their performance prospects in ...
Compound Semiconductor

Has 2D transistors' performance been inflated?

The research 'Impact of Contact Gating on Scaling of Monolayer 2D Transistors Using a Symmetric Dual-Gate Structure' appeared ...
Nanowerk

Common lab design inflates 2D transistor performance by up to six times

Lab architecture used to test 2D semiconductors artificially boosts performance metrics, making it harder to assess whether ...
Semiconductor Engineering

CFETs with Optimized Buried Power Rails

A technical paper titled “Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET)” was published by researchers at Korea University and Sungkyunkwan University.
EDN

5-Channel, Low Power Transistor Array

The CPC5608 is a 5-channel, low power transistor array integrated circuit featuring extremely low static current draw from power supply in a simple 2-state logic control input. It has two state ...
EDN

Distributing Moore’s Law to 10 nm and beyond

Moore’s Law is an observation made by Intel founder Gordon Moore that the number of transistors on an IC doubles approximately each 24 months, and the distance between transistors is inversely ...
Semiconductor Engineering

Benefits Of The Ultra-Low Leakage Currents from IGZO TFTs For Neuromorphic Applications

A new technical paper titled “A tunable multi-timescale Indium-Gallium-Zinc-Oxide thin-film transistor neuron towards hybrid solutions for spiking neuromorphic applications” was published by ...