Aimed at allowing semiconductor circuit designers to reduce the time and cost to develop resolution enhancement techniques (RET) and optical proximity correction (OPC) processes, San Jose-based ...
Unknown to most IC designers, IC layouts have been undergoing a dramatic revolution in recent years. This is happening because, in order to meet the increasingly aggressive requirements of Moore's Law ...
Nanometer designs require new approaches to silicon-to-layout verification (SVL). Widespread use of resolution enhancement technology (RET) techniques has led to far ...
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